What is clearly required for effective verification is a language-independent, very flexible and open verification integration platform that fully enfolds a wide variety of powerful technologies. Key simulation-based technologies needed for effective verification include bus-functional modeling capability; protocol monitors and checkers; transaction generation and sequencing; signal and transaction-level analysis; assertions and rule checking; functional coverage; signal and transaction-level visualization; debuggers; and HDL simulation. In addition, integration of a wide variety of custom verification modules (instruction-set simulators, intellectual property, custom GUIs and so on) is required.

Some believe that the best approach for solving simulation-based verification problems is to embed a large number of verification technologies into a single language. I believe a more effective method, however, is to provide a number of separate, key technologies that are tightly integrated around a flexible, open platform. That approach allows EDA vendors to supply their own key verification technologies, integrate best-in-class partner technologies and provide custom solutions to meet client requirements. It also allows for the delivery of multiple tools that provide similar functionality, leaving the choice of language or tool to the user.

This kind of multilanguage, multitool approach is well-known in the software development world. For example, there are many software engineers whose primary language is C++, but who will not hesitate to use Perl, Shell scripts or Make files where each serves best. Sure, it is possible to implement all of those tasks in C++, but if a designer had to write all of his Make files as C++ applications, he would probably shoot himself. Sometimes designers need performance, but at other times, they need the productivity those specialized tools and languages provide.

The same is true in hardware verification. Design engineers working at the block level often need productivity more than performance. Their primary task (especially in their own eyes) is to design silicon. Verification is a necessary evil. Designers greatly appreciate tools that help them get through that task efficiently, and a turnkey application will be the most productive solution. On the other hand, verification engineers working at the system level have different requirements. They are used to working with much more complex simulation environments, and they require very high performance. They often have more training in verification than their designer colleagues, and usually have at least one component of their verification system that requires custom integration (an instruction-set simulator or a C++ IP module, for example).

However, the similarities in the technologies those two types of engineers require are far more remarkable than the differences. There are enormous opportunities for reuse between the different levels of verification, but only if the tools and technologies that are used at each level are integrated so as to make that feasible. A flexible, open verification integration platform combined with a wide variety of verification technology modules is the key to successful, reusable verification.

Sean Dart is the vice president of engineering at Forte Design Systems Inc. (Santa Clara, Calif.). Dart previously served as chief technical officer of Speed Electronic SA. He has also held various software-engineering positions at AT&T/Olivetti, Time Office Computers and Standard Telephones and Cables.